1 Appendix E: Detector System Design Detail

 

1.1 HAWAII-2 Detector Signals

 

There are 128 connections brought out to the detector ceramic chip carrier. Table 1 provides a list of these connections.

Table 1: HAWAII-2 Detector Electrical Interface Requirements.

Signal Name

Description

Type

# of pins

Voltage Range

VDD

Digital high

Power

4

5.0 V

VSS

Digital low

Power

4

0.0 V

MUXSUB

Multiplexer substrate

Power

4

0.0 V

VDDA

Analog high

Power

4

5.0 V

DSUB

Detector substrate

Power

4

0.0 V

DRAIN

Amp drain voltage, pulled up to VDDA internally

Power

4

0.0 V

CELLDRAIN

Analog low in the unit cell

Power

4

0.0 V

CLK1

Clock for horizontal register (Pixel)

Clock

4

0.0-5.0 V

CLKB1

Clock for horizontal register (Pixel)

Clock

4

0.0-5.0 V

CLK2

Clock for horizontal register (Pixel)

Clock

4

0.0-5.0 V

CLKB2

Clock for horizontal register (Pixel)

Clock

4

0.0-5.0 V

VCLK

Master clock for the vertical register

Clock

4

0.0-5.0 V

LSYNC

External line sync

Clock

4

0.0-5.0 V

FSYNC

External frame sync

Clock

4

0.0-5.0 V

RESET

Control signal for resetting all the pixels

Clock

4

0.0-5.0 V

READ

Control signal for the readout

Clock

4

0.0-5.0 V

O1

Control signal for the output option

Clock

4

0.0-5.0 V

O2

Control signal for the output option

Clock

4

0.0-5.0 V

LRST

Reset for horizontal shift register

Clock

4

0.0-5.0 V

RESETEN

Optional control signal to reset the column bus to CELLDRAIN while no readout

Clock

4

0.0-5.0 V

BIASPWR

Source voltage of bias P-FET

Bias

4

5.0 V

BIASGATE

Gate voltage of bias P-FET

Bias

4

3.3-3.8 V

VRESET

Zero signal reference in the cell

Bias

4

0.5-1.0 V

OUTPUT[1:8]

The final outputs for 8 buses

Output

32

10 K pullup to 5.0 V

OUTPUT9

Output of reference signal

Output

4

 10 K pullup to 5.0 V

LINECHK

Horizontal testing signal output when TESTEN = high

Test Pad

0

 

FRAMECHK

Vertical testing signal having output when TESTEN = high

Test Pad

0

 

TESTEN

The control signal for testing, pulled down to MUXSUB internally

Test Pad

4

 

Total

 

 

128

 

 

NOTE: All biases should be bypassed with 0.1 μF ceramic/metal film capacitors. BIASGATE and VRESET should also have 4.7 μF tantalum capacitors in parallel with the 0.1 μF ceramic/metal film capacitors.

 

1.2 General Description of HAWAII-2 Detector

 

The following description of the HAWAII-2 detector is extracted from the Rockwell WWW web pages.

 

The HAWAII-2, 2048×2048 readout is very similar to that of the HAWAII readout with a few critical differences. The HAWAII-2 has four independent quadrants with outputs of either 1 per quadrant or 8 per quadrant. There are thirteen CMOS-level control signals, two 5 V power supplies (one analog and one digital), and three biases. The multiplexer architecture has been optimised to minimise glow. Dark current of < 0.05 e-/s and read noise of < 10 e- should be achieved due to refinements in the readout design to suppress the pixel reset anomaly associated with earlier astronomy arrays such as NICMOS3.Each quadrant contains two digital shift registers for addressing the pixels in the array; a horizontal register, and a vertical register. The horizontal register requires five(5) clocks, the vertical requires only two(2) clocks. To obtain a raster scan output, the horizontal register is clocked in the fast direction with the vertical register being clocked in the slow direction. Refer to Figure 1 for timing signal diagram.

 

1.2.1 Horizontal Register

 

The basic clocks for the horizontal register include CLK1, CLK2, CLKB1, CLKB2, and LSYNC. This is a change relative to the HAWAII multiplexer to reduce clock driver glow. In this case, the two clock phases should be overlapping with rise times < 100 ns. The clocking is effectively not changed relative to the HAWAII mux where CLK1=CLKB2, CLK2=CLKB1, and CLK1 is complimentary to CLK2 within 25 ns. There is now also one full clock cycle per pixel, i.e. two clock edges per pixel. The multiple external clocks allow us to eliminate the horizontal clock. When LSYNC is low, the register is reset, when LSYNC goes high, the register is released and a single bit starts shifting down the register. Note: CLK1 must be low when LSYNC transitions low. LRST is the reset for the horizontal register used when in the 8 output shuffled mode. This signal should be held at 5 V when not using this mode as in the case for NIFS.

 

1.2.2 Vertical Register

 

The vertical register is controlled as before in the HAWAII mux. by two external clocks, FSYNC and VCLK. FSYNC is a reset similar to LSYNC with it being active low and pulsed once every frame. VCLK is the fast clock for the vertical register that propagates the FSYNC pulse down the vertical shift register. VCLK takes the place of LINE clock used in the HAWAII multiplexer. A single positive pulse on VCLK advances the mux one row. Note: VCLK must be low when FSYNC transitions low.

 

1.2.3 Reset and Read

 

The two remaining clocks are RESET and READ. These two clocks are used to gate with the vertical register outputs to form the line reset and read function of the multiplexer. RESET is an active high (unlike the HAWAII mux) clock, which will reset all of the detectors in the selected row to the voltage set by VRESET (supplied externally off chip). Resetting the array requires addressing the desired row to reset using the shift register and 'pulsing' the RESET clock "high" or above 4.2 V for a minimum of 250 ns for normal operation and a minimum of 100 ns for fast clocking. The READ clock is "active high" which will allow signals from the current row to be transferred to the column (vertical) bus. The column buses are inputs to horizontal register controlled transmission gates. The output of the transmission gates is the horizontal bus, which is the input to the output source follower(SF) amplifier.

 

1.2.4 Double Correlated Sampling

 

Double Correlated Sampling (DCS) is a clocking method by which the array is reset, sampled, allowed to integrate, and re-sampled. The difference between the 1st and 2nd samples is then recorded. DCS is effective in reducing noise and eliminating detector offsets. For long integration times, IR glow from the output source follower amplifiers will be evident in the image as high dark current areas in the areas close to the output SF amplifiers. Self-emission from the output SF can be minimized by turning off the conduction through the amplifiers during integration via the READ signal. Modifications to the locations of the output SF have been made to also reduce the problems associated with “glow”.

 

Turning off the SF amplifiers can be accomplished by ensuring that the gate of the of the unit cell access P-FET is pulled “high” when not in use. This occurs when the READ input clock is “low”, hence disconnecting all of the column buses from the gate of the source follower amplifier. The gate will be pulled up via the BIASPWR bias input. Even though an external amplifier will be used, the READ signal may still be required to reduce dissipation in the external amplifier. Measurements will need to be carried out to determine whether having the external amplifier on or off minimizes drift. In the case where the amplifier is off, the gate of the external amplifier will be pulled high by the external 200 KΩ bus load resistor.

 

1.2.5 Biases/Power Supplies

 

There are only two biases that may need to be adjusted when using the output source follower amplifier, BIASGATE and VRESET. BIASGATE is the gate voltage of the “pull-up” P-FET for the cell source follower and BIASPWR is the source voltage of the P-FET. Regulating BIASGATE adjusts the speed and the dynamic range of the unit cell source follower. As the “pull-up” P-FET is not used with an external amplifier in the NIFS case, BIASGATE is not connected and no adjustment is needed. VRESET is the reset voltage that gets applied to the detectors during the reset operation. The voltage is applied through a N-FET reset switch, this has an associated voltage drop due to parasitics and will reduce the actual voltage to the detector by about 50-100 mV. VRESET is usually operated in the 0.5 V to 1.0 V range with DSUB at 0 V for PACE-1 detectors. VRESET and DSUB will have to be changed when using a MBE or p-on-n detector architecture.

 

1.2.6 Output Modes

 

There are three output modes, controlled by digital controls O1 and O2:

Single Output Mode. Option 1 is selected when O1 =1 and O2 = 0. In this case all data from each quadrant is routed through OUPUT1.

Eight Output, Unshuffled Mode. Option 2 is selected when O1 = 0 and O2 = 0. In this case, the data from each quadrant is spread across the eight outputs OUTPUT[1:8]. Each output provides data from 128 consecutive columns.

Eight Output, Shuffled Mode. Option 3 is selected when O1 = 0 and O2 = 1. This is similar to option 2, except that each frame of data from each group of 128 columns is cyclically shifted to the next output bus. This pattern is synchronized by LRST, which when low keeps the initial pattern. Basically pulsing it once starts the process, it then keeps cycling.

 

For NIFS, only Single Output Mode is required therefore O1 =1 and O2 = 0.

 

Output9 is a reference output that is connected to the VRESET bias and will mirror any variations in this signal. The reference signal comes out on the 1025th pixel clock; therefore the array must be over-clocked by a minimum of 1 pixel, but can be more. The reference output duration is one pixel time. Output9 requires a pull-up resistor to supply current; a 10 kohm resistor to 5 V is typically used.

 

Users have a choice of using the on-chip source follower amplifier or using an external amplifier. Both signals are located on the output pads and are controlled with the DRAIN signal. By holding DRAIN at 0 V the SF amplifier is enabled, raising the voltage to 5 V bypasses the SF amplifier, enabling use of an external FET. For NIFS, the DRAIN signal should be set to 5 V, thus bypassing the SF amplifier.

 

1.2.7 Test Points

 

The digital test points, LINECHK and FRAMECHK, are enabled by TESTEN. This is internally held low in the absence of an external signal. This is also to minimize glow.

 

1.2.8 Crosstalk Reduction

 

When RESETEN is high, the column buses are clamped to CELLDRAIN whenever they are not being driven by pixels. If RESETEN is low, the buses are left floating when not being driven, as is the case with the original HAWAII. This is an attempt to address some of the low-level crosstalk observed by astronomers.

 

Figure 1: 2048×2048 HAWAII-2 basic timing for single output mode.

 

 

1.3 SDSU-2 Detector Controller Components Purchased.

 

The list of components and prices for the SDSU-2 Detector Controller is shown in Table 2. These components are sourced from Bob Leach. All units have the capability to operate from 120 VAC at 50 Hz and 60 Hz as well as 240 VAC at 50 Hz for testing at RSAA.

 

Table 2: SDSU-2 Detector Controller Components.

 

 

1.4 Non-Destructive Read Noise Reduction Algorithm

 

Non-destructive read noise reduction algorithm works by taking multiple reads of the pixel value during the exposure time and finding the slope of the best fitting straight line through the points using a least square fit. The algorithm (Chapman et al. 1990) to find the slope is

where Vi is the pixel value of sample i, n is the total number of samples, and dt is the time interval between samples. This is a much reduced form of the usual straight line fitting algorithm as it takes into account the fact that the values for t are all at fixed intervals which is known in advance.

 

The reduction in read noise for large n (Chapman et al. 1990) is described by

where σr is the read noise associated with a single read and σre is the equivalent read noise given by the noise reduction algorithm.

 

1.5 Lake Shore Model 340 Temperature Controller Specification

 

The specifications of the Lake Shore Model 340 Temperature Controller are described in Table 3.

 

Table 3: Lake Shore Model 340 Temperature Controller Specification.

Thermometry

 

Number of Inputs

Two included (additional inputs optional)

Measurement Type

4-lead Differential

A/D Resolution

24-bit analog-to-digital

Update Rate

Up to 20 readings/second on an input, 40 readings/second on all inputs

Control

 

Control Loops

Two

Control Type

Digital PID with manual output

Heater Output (Loop 1 Only)

 

Heater Output Type

Variable DC current source

Heater Output Resolution

18-bit digital-to-analog converter

Max Heater Output Power

100 W

Max Heater Output Current

2 A

Current Limit Settings

2 A, 1 A, 0.5 A, 0.25 A

Heater Output Compliance

50 V

Heater Output Ranges

5 decade steps in power

Heater Connector

Three banana plugs (Hi, Lo, Shield)

Heater Load Type

Resistive

 

 

Heater Noise

50 μV + 0.001% of output voltage

Heater Output (Loop 2 Only)

 

Output

Analog Output 2

Heater Output Type

Variable DC voltage 0 to 10 V

Heater Output Resolution

1.25 mV

Max Heater Output Current

100 mA

Max Heater Power (100ohm load)

1 W

Heater Connector

BNC

Heater Load Type

Resistive

Heater Load Range

Greater than 100 ohm, 100 ohm  for max heater power

PID Control Settings

 

Gain (Proportional)

0-1000 with 0.1 setting resolution

Reset (Integral)

1-1000 with 0.1 setting resolution

Rate (Derivative)

1-1000 s with 1 s resolution

Rate (Derivative)

1-1000 s with 1 s resolution

Zone Control Mode

10 temperature zones with control parameters

Ramping

Setpoint ramping at user specified rate

Front Panel

 

Number of Input Displays

One to eight

Display units

Temperature in K, C, or sensor units

Display Resolution Input Temperature

0.0001 K below 10 K, 0.001 K above 10 K

Heater Output Display

Numeric display in percent of full scale for power or current. Bar graph display of Heater Output available

Interfaces

 

IEEE-488.2 Interface

SH1, AH1, T5, L4, SR1, RL1, PP0, DC1, DT0, C0, E1

Serial Interface

RS-232C electrical format, 19,200 baud, RJ-11 connector

General

 

Ambient Temperature Range

20-30 C (68-86 F) for specified accuracy; 15-35 C (59-95 F) for reduced accuracy

Power Requirements

100, 120, 220, 240 VAC (+ 5%, -10%), 50 or 60 Hz; 200 VA

Enclosure Type

Full 19-inch rack mount

Size

431.8 mm × 88.9 mm × 381 mm (17" × 3.5" × 15")

Weight

11.4 kilograms (25 pounds)

 

 

1.6 Lake Shore Model 340 Temperature Controller Purchased Items

 

Table 4 lists the Lake Shore Model 340 Temperature Controller items purchased.

 

Table 4: Temperature Controller Items Purchased.

Item

Description

Model 340

Temperature controller

3462 Dual Standard Input Option Card.

Adds two standard inputs to Model 340. The card has separate A/D's and excitation for each sensor. A microprocessor on the card manages the A/D and communication with Model 340. The card allows the Model 340 to read four sensors and use any of the sensors as a control sensor.

3003 Heater Output Conditioner

Unit that provides passive filtering to reduce the heater output noise. The typical insertion loss is 20 dB at or above line frequency and > 40 dB at or above double line frequency. A 144 mm × 72 mm × 165 mm panel mount enclosure houses this option, and it weighs 1.6 kg.

RM-1 Rack Mounting Kit

Mounting brackets, ears, and handles for 19" rack mounting.

 

 

1.7 Temperature Test Dewar Results

 

A test dewar was wired up as shown in Figure 2 to assess the performance of the proposed temperature control system consisting of the Lake Shore Model 340 temperature controller, Cernox CX1080-LR-20L sensor, and Vishay RTO heater resistor. The test dewar consisted of a 85 mm × 15 mm × 6 mm copper block mounted inside a RSAA standard liquid nitrogen dewar. Various holes were machined in this block to provide mounting locations for the temperature sensors, heaters, and cooling straps. The setup consisted of mounting four Lake shore temperature sensors (one Cernox CX-1080-LR and three silicon diode DT471-CU) and three heater resistors as follows:

 

1)       To control the temperature of the block, one Vishay RTO 47 Ω heater resistor was sandwiched between the cooling strap attaching to the block and the test copper block itself. A CX-1080-LR temperature sensor was mounted in a hole as close as practical to this attachment point using a grub screw.

2)       To measure the thermal temperature lag of the block, a silicon diode DT471-CU temperature sensor was mounted 40 mm distance from the cooling strap attachment point.

3)       To simulate the power dissipation in the detector during readout, a 1 kΩ Vishay RTO heater was mounted towards the end of the block 25 mm from the cooling strap attachment point.

4)       To determine how a disturbance through the cooling strap will affect the temperature control of the test block, a 100 Ω Vishay RTO heater resistor and a DT471-CU temperature sensor were mounted mid way along the cold strap on a small copper block.

5)       To measure the cold work surface temperature, a silicon diode DT471-CU was mounted on the cold work surface.

 

The four temperature sensors and the 47 Ω and 100 Ω heaters were wired to the Lake Shore Model 340 temperature controller using shielded individual twisted pair cables. Extreme care with grounding and shielding was exercised with the wiring to reduce the possibility of noise being introduced into the low level signals needed for milliKelvin level temperature control. The temperature log program, lakelog, was used to monitor the four temperature sensors and the two heater resistors.

 

Figure 2: Block diagram of setup for temperature tests.

 

Demonstration of milliKelvin control was discussed in §Error! Reference source not found.. As described above, additional heater resistors were added to the test setup to observe the response of the system while under servo-control to various disturbances such as the disturbance caused by the power dissipation in the detector during readout and disturbances that may occur through the cold strap. The following sections summarize the result of these disturbance tests.

 

1.7.1  Detector Dissipation Disturbance Response

 

The power dissipation in the detector is due mainly to the clocking of the multiplexer and is specified by Rockwell to be 2 mW. In normal operation, it is expected that the multiplexer will be clocked for 10 s every minute or two. To investigate the response of the control loop to this type of disturbance, a step disturbance of 2 mW was applied to the copper block using the 1 kΩ heater resistor on the test block. The copper block response, shown in Figure 3, shows that the 2 mW disturbance applied at time equals 21 s has no effect on the control loop temperature. In fact, after doing additional tests it was found that it took a disturbance of greater than 8 mW to have any effect.

 

Figure 3: Copper block temperature response to 2 mW step detector disturbance.

 

 

1.7.2 Cold Strap Disturbance Response

 

To investigate the response of the control loop to disturbances through the cold strap, the temperature of the small copper block mid way along the cold strap was ramped as shown in Figure 5. The rate of change in temperature of this disturbance is greater than expected in NIFS. The response, in Figure 4, shows no signs of the disturbance and thus demonstrates that the control loop can easily handle this type of disturbance.

 

Figure 4: Test block temperature response to ramped cold strap disturbance.

 

Figure 5: Temperature of cold strap block during ramped cold strap disturbance.

 

 

1.8 Fringing

 

1.8.1 Physical Nature of Fringing

 

HAWAII-2 PACE detectors are manufactured by depositing the HgCdTe detector layer on a sapphire substrate. The science field is viewed through this substrate. Multiple reflections within the sapphire substrate cause optical interference which imposes a modulation on the measured light intensity. Being a spectrograph, NIFS will illuminate each pixel of the detector in the dispersion direction with light of different wavelengths. To first order, the fringing pattern can be considered to be caused by light of different wavelengths interfering at normal incidence in a layer of constant thickness. Light at different wavelengths actually originates from the grating pupil so the chief rays actually strike the detector at incident angles of up to ~ 3.6°. This causes a slight deviation from the first order pattern.

 

The wavelength of light focusing on each detector pixels is given by the grating equation

where m is the grating order, a is the grating groove density in l/mm, a is the incident angle at the grating, and β is the diffracted angle at the grating. All NIFS gratings work in first order (§Error! Reference source not found.). The incident angle and on-axis reflected angle, β0, can be expressed in terms of the grating angle, θ, and the Ebert angle, φ, as

The Ebert angle in NIFS is φ = 30º, and the operating angles for the NIFS gratings are listed in Error! Reference source not found.. The diffracted angle corresponding to each detector pixel is defined geometrically by the camera focal length of 288 mm and the detector pixel size of 18 μm.

 

Light under-going multiple reflections in the sapphire substrate will constructively interfere when the optical path difference between adjacent transmitted beams is an integral number of wavelengths. This occurs when

where m is now the interference order, n is the refractive index of the sapphire substrate (~1.74), d is the thickness of the sapphire substrate, γ′ is the incident angle within the sapphire substrate, and n′ is the refractive index in the HgCdTe detector material. We have no data on the refractive index of HgCdTe at near-infrared wavelengths, but this is of little consequence because the incident angles, g' are small. The analysis is simplified by assuming that n′ = 1.0. The interference equation then reduces to the familiar Fabry-Perot equation

Constructive interference occurs at integral values of m and destructive interference occurs at half-integral values of m.

 

1.8.2 Fringe Period

 

Fringing effects in NIFS have been modeled by calculating the interference order, m, across the detector for each of the NIFS gratings (Figure 6 to Figure 10). A sapphire substrate thickness of 0.015 inches has been assumed.

 

Figure 6: Interference order vs wavelength for the Z grating.

 

Figure 7: Interference order vs wavelength for the J grating.

 

Figure 8: Interference order vs wavelength for the H grating.

Figure 9: Interference order vs wavelength for the K grating (short wavelength setting).

 

Figure 10: Interference order vs wavelength for the K grating (long wavelength setting).

 

 

1.8.3 Fringe Correction

 

In principle, the modulation due to fringing can be corrected through division by a suitable flatfield frame. In practice, it is difficult to ensure that the flatfield lamp illuminates the NIFS integral-field unit (IFU) in exactly the same way as does the science object. In addition, small amounts of flexure between the science exposure and the flatfield exposure will cause incomplete cancellation.

 

The effect of flexure on fringing correction has been simulated by dividing a model fringe pattern by a shifted flatfield spectrum. The maximum peak-to-valley amplitude in the corrected spectrum is listed in Table 5 to Table 9 for each of the NIFS gratings. NIFS is required to have a flexure of < 0.1 pixel per 15° change in attitude. We may expect a flexure of ~ 0.2 pixels between a flatfield frame taken at twilight and a typical science frame. Hodapp et al. (1996) report a peak-to-valley modulation of ~ 10% in the uncorrected fringe pattern with KSPEC and a HAWAII-1 array. If the HAWAII-2 array is similar, we expect a maximum peak-to-valley variation in corrected NIFS spectra due to flexure of ~ 1.3%, 0.9%, 0.8%, 0.6%, and 0.5% with the Z, J, H, Ks, and Kl grating settings, respectively. Illumination differences between the flatfield and science frames may increase these residuals.

 

Table 5: Percentage Residual Maximum p-v Modulation for Z Grating.

% Fringe

Amplitude

(p-v)

Flexure shift (pixels)

0.1

0.2

0.5

1.0

1.5

2.0

100

11.8

22.5

53.5

99.0

139.5

177.2

80

8.0

15.4

37.1

69.9

99.2

126.7

60

5.2

10.1

24.7

47.2

67.7

87.2

40

3.0

6.0

14.8

28.7

41.8

54.3

20

1.4

2.7

6.7

13.3

19.6

25.8

10

0.7

1.3

3.2

6.4

9.5

12.6

 

Table 6: Percentage Residual Maximum p-v Modulation for J Grating.

% Fringe

Amplitude

(p-v)

Flexure shift (pixels)

0.1

0.2

0.5

1.0

1.5

2.0

100

8.0

15.5

37.6

69.8

100.1

126.7

80

5.4

10.5

25.9

48.8

70.6

90.1

60

3.5

6.9

17.0

32.7

47.7

61.4

40

2.1

4.1

10.1

19.7

29.1

37.8

20

0.9

1.8

4.6

9.0

13.4

17.7

10

0.4

0.9

2.2

4.3

6.5

8.6

 

Table 7: Percentage Residual Maximum p-v Modulation for H Grating.

% Fringe

Amplitude

(p-v)

Flexure shift (pixels)

0.1

0.2

0.5

1.0

1.5

2.0

100

7.1

14.2

33.8

63.1

90.1

114.8

80

4.8

9.6

23.2

44.1

63.5

81.6

60

3.1

6.2

15.2

29.4

42.7

55.5

40

1.8

3.7

9.0

17.7

26.0

34.1

20

0.8

1.7

4.1

8.1

12.0

15.8

10

0.4

0.8

2.0

3.9

5.8

7.7

 

Table 8: Percentage Residual Maximum p-v Modulation for Ks Grating Setting.

% Fringe

Amplitude

(p-v)

Flexure shift (pixels)

0.1

0.2

0.5

1.0

1.5

2.0

100

5.5

11.0

26.7

50.7

72.8

93.4

80

3.7

7.5

18.3

35.2

51.1

66.0

60

2.4

4.9

12.0

23.4

34.3

44.6

40

1.4

2.9

7.1

14.0

20.7

27.1

20

0.6

1.3

3.2

6.4

9.5

12.5

10

0.3

0.6

1.5

3.0

4.6

6.0

 

Table 9: Percentage Residual Maximum p-v Modulation for Kl Grating Setting.

% Fringe

Amplitude

(p-v)

Flexure shift (pixels)

0.1

0.2

0.5

1.0

1.5

2.0

100

4.9

9.7

23.1

44.7

63.4

82.9

80

3.3

6.6

15.9