Gemini Near-Infrared Integral-Field Spectrograph (NIFS)
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Appendix: Detector System Design Data
16.1 Outgassing
A good source of outgassing data can be found at Goddards Space Flight Center Material Branch[1]. The following terms are used to define outgassing.
16.1.1 Total Mass Loss (TML)
The mass loss of the sample, determined from the weights before and after the 398 K exposure, expressed as a percentage. A sample with low outgassing will have TML £ 1.0%.
16.1.2 Collected Volatile Condensable Material (CVCM)
The difference between the weight of a clean collector and of the collector having condensed materials will provide the mass of condensables A sample with low outgassing will have CVCM £ 0.10%.
16.2 Flex Circuit Capacitance Calculations
A calculator for calculating capacitance and impedance for various strip lines can be found at http://www.automata.com/engtools/impednce/imphome.htm. The results for both standard and embedded flex circuits of various lengths and materials are detailed in Table 11 and Table 12. A mathcad program for calculating capacitance and impedance can be downloaded from http://www.sigcon.com/design.htm. Figure 1 and Figure 2 define the micro strip dimension parameters used in Table 11 and Table 12, respectively.
Table 11: Capacitance and Impedance of Standard Microstrip Flex Circuits
|
|
h (mils) |
t (Oz) |
W (mils) |
Er Dielectric constant |
Impedance (OHM) |
Capacitance (pF/cm) |
Capacitance for 18 cm length (pF) |
Capacitance for 55 cm length (pF) |
|
Teflon |
5.2 |
1 |
4 |
2.95 |
81 |
0.7 |
12 |
39 |
|
Kapton |
5 |
1 |
4 |
4.5 |
65 |
1.1 |
19 |
61 |
|
Kapton |
2 |
1 |
4 |
4.5 |
44 |
1.6 |
28 |
88 |
Figure 1: Standard microstrip dimension parameters used in Table 11.
Table 12: Capacitance and Impedance of Embedded Microstrip Flex Circuits
|
|
h (mils) |
t (Oz) |
W (mils) |
Er Dielectric constant |
Impedance (OHM) |
Capacitance (pF/cm) |
Capacitance for 18 cm length (pF) |
Capacitance for 55 cm length (pF) |
|
Teflon |
5.2 |
1 |
4 |
2.95 |
81 |
0.7 |
12 |
39 |
|
Kapton |
5 |
1 |
4 |
4.5 |
65 |
1.1 |
19 |
61 |
|
Kapton |
2 |
1 |
4 |
4.5 |
45 |
1.6 |
29 |
89 |
Figure 2: Embedded microstrip dimension parameters used in Table 12.
16.3 Detector Output Amplifier Settling Time Calculations
The slew rate settling time, TS, for the detector output amplifier is given by
where C is the line capacitance, VS is the maximum output voltage swing (~VRESET), and IL is the load current. Table 13 lists settling times for various combinations of capacitance and load currents.
Table 13: Detector Output Amplifier Settling Times
|
Maximum Output Voltage
Swing |
Capacitance |
Load Current |
Slew Rate Settling Time |
|
(V) |
(pF) |
(mA) |
(ms) |
|
|
|
|
|
|
1.0 |
21 |
100 |
0.21 |
|
1.0 |
37 |
100 |
0.37 |
|
1.0 |
48 |
100 |
0.48 |
|
1.0 |
97 |
100 |
0.97 |
16.4 HAWAII-2 Detector Signals
There are 128 signals brought out to the detector ceramic chip carrier. Table 14 provides a list of these signals. This table gives a first pass attempt at defining the minimum number of pins required to be connected to the detector controller.
Table 14: HAWAII-2 Detector Electrical Interface Requirements
|
Signal Name |
Description |
Type |
# of pins |
Min # of pins |
Voltage Range |
|
VDD |
Digital high |
Power |
4 |
1 |
5.0 V |
|
VSS |
Digital low |
Power |
4 |
1 |
0.0 V |
|
MUXSUB |
Multiplexer substrate |
Power |
4 |
? |
0.0 V |
|
VDDA |
Analog high |
Power |
4 |
1 |
5.0 V |
|
DSUB |
Detector substrate |
Power |
4 |
1 |
0.0 V |
|
DRAIN |
Amp drain voltage, pulled up to VDDA internally |
Power |
4 |
? |
0.0 V |
|
CELLDRAIN |
Analog low in the unit cell |
Power |
4 |
? |
0.0 V |
|
CLK1 |
Clock for horizontal register (Pixel) |
Clock |
4 |
1 |
0.0-5.0 V |
|
CLKB1 |
Clock for horizontal register (Pixel) |
Clock |
4 |
1 |
0.0-5.0 V |
|
CLK2 |
Clock for horizontal register (Pixel) |
Clock |
4 |
1 |
0.0-5.0 V |
|
CLKB2 |
Clock for horizontal register (Pixel) |
Clock |
4 |
1 |
0.0-5.0 V |
|
VCLK |
Master clock for the vertical register |
Clock |
4 |
1 |
0.0-5.0 V |
|
LSYNC |
External line sync |
Clock |
4 |
1 |
0.0-5.0 V |
|
FSYNC |
External frame sync |
Clock |
4 |
1 |
0.0-5.0 V |
|
RESET |
Control signal for resetting all the pixels |
Clock |
4 |
1 |
0.0-5.0 V |
|
READ |
Control signal for the readout |
Clock |
4 |
1 |
0.0-5.0 V |
|
O1 |
Control signal for the output option |
Clock |
4 |
0 |
0.0-5.0 V |
|
O2 |
Control signal for the output option |
Clock |
4 |
0 |
0.0-5.0 V |
|
LRST |
Reset for horizontal shift register |
Clock |
4 |
1 |
0.0-5.0 V |
|
RESETEN |
Optional control signal to reset the column bus to CELLDRAIN while no readout |
Clock |
4 |
1 |
0.0-5.0 V |
|
BIASPWR |
Source voltage of bias P-FET |
Bias |
4 |
4 |
5.0 V |
|
BIASGATE |
Gate voltage of bias P-FET |
Bias |
4 |
4 |
3.3-3.8 V |
|
VRESET |
Zero signal reference in the cell |
Bias |
4 |
4 |
0.5-1.0 V |
|
OUTPUT[1:8] |
The final outputs for 8 buses |
Output |
32 |
4 |
10 K pullup to 5.0 V |
|
OUTPUT9 |
Output of reference signal |
Output |
4 |
4 |
|
|
LINECHK |
Horizontal testing signal output when TESTEN = high |
Test Pad |
0 |
0 |
|
|
FRAMECHK |
Vertical testing signal having output when TESTEN = high |
Test Pad |
0 |
0 |
|
|
TESTEN |
The control signal for testing, pulled down to MUXSUB internally |
Test Pad |
4 |
|
|
|
Total |
|
|
128 |
35 |
|
NOTE: All biases should be bypassed with 0.1 µF ceramic/metal film capacitors. BIASGATE and VRESET should also have 4.7 µF tantalum capacitors in parallel with the 0.1 µF-ceramic/metal film capacitors.
16.5 General Description of HAWAII-2 Detector
The following description of the HAWAII-2 detector is extracted from the Rockwell WWW web pages.
The HAWAII-2 2048´2048 readout is very similar to that of the HAWAII readout with a few critical differences. The HAWAII-2 has four independent quadrants with outputs of either 1/quad or 8/quad. There are thirteen CMOS-level control signals, two 5 V power supplies (one analog and one digital), and three dc biases. The multiplexer architecture has been optimized to minimize glow. The dark current goal of < 0.05 e/s should be achieved using correlated double sampling. Read noise of < 10 e has also been achieved due to refinements in the readout design to suppress the pixel reset anomaly associated with earlier astronomy detectors such as NICMOS3.
Each quadrant contains two digital shift registers for addressing pixels in the detector; a horizontal register and a vertical register. The horizontal register require 5 clocks, The vertical register requires only 2 clocks. To obtain a raster scan output, the horizontal register is usually clocked in the fast direction with the vertical register being clocked in the slow direction.
16.5.1 Horizontal Register
The basic clocks for the horizontal register include CLK1, CLK2, CLKB1, BLKB2 and LSYNC. This is a change relative to the HAWAII multiplexer to reduce clock driver glow. In this case, the two clock phases should be non-overlapping. The clocking is effectively not changed relative to the HAWAII mux if single phase clocking is instead used where CLK2=CLKB1, and CLKB2=CLK1. There is now also one full clock cycle per pixel, i.e. two clock edges per pixel. The multiple external clocks allowed the horizontal clock driver to be eliminated; also, LSYNC is now a reset. When LSYNC is low, the register is reset, when LSYNC goes high, the register is released and a single bit starts shifting down the register.
16.5.2 Vertical Register
External clocks FSYNC and VCLK control the vertical register. A single positive pulse on VCLK advances the mux one row. FSYNC is a reset similar to LSYNC (active low). When FSYNC is low, the register is reset, when FSYNC goes high, the register is released and a single bit starts shifting down the register.
16.5.3 Reset and Read
The two remaining clocks are RESET and READ. These two clocks are used to gate with the vertical register outputs to form the line reset and read function of the multiplexer. RESET is an active high (unlike the HAWAII mux) clock, which will reset all of the detectors in the selected row to the voltage VRESET (supplied externally off chip). Usually, the process of resetting the detector array involves addressing the desired row to reset using the vertical shift register, and pulsing the RESET line high. The READ clock is an active high clock that will allow signals from the current row to be transferred to the column (vertical) buses. The column buses are input to horizontal register controlled transmission gates. The output of the transmission gates is the horizontal bus, which is input to the output source follower amplifier.
16.5.4 Correlated Double Sampling
Correlated Double Sampling (CDS) is a clocking method by which the detector is reset, sampled, allowed to integrate, and re-sampled with the difference between the 1st and 2nd samples being recorded. CDS is effective at reducing noise and eliminating detector offsets. For long integration times, IR glow from the output source follower amplifiers will be evident in the image as high dark current areas in the corners of the detector. The glow will be on the order of 1,000's of electrons/s but can be reduced by minimizing the output source follower conduction during integration. Turning off the source follower amplifiers can be accomplished by ensuring that the gate of the PFET output source follower is pulled high (+5V) when not in use. This occurs when the READ input clock is pulled low, hence disconnecting all of the column buses from the gate of the source follower. The gate will be pulled up via the BIASPWR bias input.
16.5.5 Biases/Power Supplies
There are only two biases that may need to be adjusted. BIASGATE is the gate voltage of the "pull-up" PFET for the cell source follower and BIASPWR is the source voltage of the PFET. BIASGATE is used to adjust the speed and dynamic range of the unit cell source follower. A trade off can be made between speed and dynamic range by adjusting BIASGATE from 3.3 V to 3.8 V. Lower voltage increases the speed at the expense of dynamic range, while higher voltage increases the dynamic range at the expense of speed. A typical BIASGATE voltage of 3.5 V is used for initial characterization of the hybrid. VRESET is the reset voltage that is applied to the detectors during the reset operation. This voltage is applied through an NFET reset switch which has an associated voltage drop across it due to parasitic of the reset FET; hence, this will reduce the actual voltage to the detector by about 100mV - 150mV. VRESET is usually operated in the 0.5V to 1.0V range.
16.5.6 Output Modes
There are three output modes, controlled by digital controls O1 and O2
Single Output Mode. Option 1 is selected when O1 = 1 and O2 = 0. In this case all data from each quadrant is ported through OUTPUT1.
Eight Output, Unshuffled Mode. Option 2 is selected when O1 = 0 and O2 = 0. In this case, the data from each quadrant is spread across the eight outputs OUTPUT[1:8]. Each output provides data from 128 consecutive columns.
Eight Output, Shuffled Mode. If O1 = 0 and O2 =1, option 3 is selected. This is similar to option 2, except that each frame of data from each group of 128 columns is cyclically shifted to the next output. This pattern is synchronized by LRST, which, when low, keeps the initial pattern. Basically, pulse it once starts the process; it then keeps cycling.
16.5.7 Test Points
The digital test points, LINECHK and FRAMECHK, are enabled by TESTEN. This is internally held low in the absence of an external signal. This is also to minimize glow.
16.5.8 Crosstalk Reduction
When RESETEN is high, the column buses are clamped to CELLDRAIN whenever they are not being driven by pixels. If RESETEN is low, the buses are left floating when not being driven, as is the case with the original HAWAII. This is an attempt to address some of the low level crosstalk problems observed by astronomers.
16.6 Description Of SDSU-2 Video Processor Board Options
The two video processor board options are the Dual Channel IR Video Processor Board and the Quad Channel Coadder Video Processor Board. These two boards will be described in the following sections.
16.6.1 Dual Channel IR Video Processor Board
The Dual Channel IR Video Processor Board provides the following features
1) Two complete video processor stages with ADC converters. The video processing stages are configured by populating the board with components to suit the target detector. Each video processor stage provides the following capability
a) Differential or single ended input. Input op-amps are AD829 and AD846.
b) Fixed gain, whose gain can be varied by appropriate selection of gain setting resistors at board construction time.
Programmable input offset circuit to remove the bias of the incoming detector signal. The range of programmable offset is configured in the following three ways
bias DAC reference jumpers JP15 and JP16 selects unipolar or bipolar offset range.
i) reference gain resistors R73 and R74 select the maximum and minimum range value of the offset
ii) summing resistors R48 and R49 select whether the offset is added or subtracted from the incoming detector signal
c) An ADS-937 S/H switch and ADC converter which operates over a range of 0 to -10V.
2) Six programmable DC biases which have the following jumper selectable voltage ranges 0 to +5V, 0 to -5V or -5V to +5V. They are controlled by 12-bit DACs and can be set to within ~ 3mV. Their long term stability is about 2 mV, and their noise is less than one mV rms if connected to the input of the video processor board.
The digital data from the ADC converters (image data) transferred in the same manner as for CCD video board. This is done by either of the following two methods
a) Slow data reading. In this method, the data is transferred by the timing Digital Signal Processor, DSP, the data is read over the backplane one pixel and one board at a time, and then written one pixel at a time to the host computer. Data transferred this way by the DSP is very slow and would only be done when some preprocessing of the data is required by the timing DSP.
b) Fast data reading. This is the more normal way to read data. This method uses a separate image data path that bypasses the DSP and transfers images to the host computer at the same time as DSP is doing timing functions.
16.6.2 Quad Channel Coadder Video Processor Board
The Quad Channel Coadder Video Processor Board provides the following features
1) Four complete video processor stages and ADC converters. The video processing stages are configured by populating the board with components to suit the detector. Each video processor chain provides the following capability
a) Differential or single ended input. Input op-amp is AD829.
b) Fixed gain whose gain can be varied by appropriate selection of gain setting resistors at board construction time.
c) Programmable input offset circuit to remove the bias of the incoming detector signal. The range of programmable offset is configured in the following three ways
i) bias DAC reference jumpers JP15 and JP16 selects unipolar or bipolar offset range.
ii) reference gain resistors R73 and R74 select the maximum and minimum value of the offset.
iii) summing resistors R48 and R49 select whether the offset is added or subtracted from the incoming detector signal.
d) An ADS-937 S/H switch and ADC converter which operates over a range of 0 to -10V.
2) There is no bias generating circuit and biases will need to be supplied from the clock board.
3) Digital signal processing capability using the following hardware. A 1Kx16bit input FIFO to buffer ADC data before inputting to a 75 MHz Motorola DSP56002 DSP with one Megaword (32 bit wide) SRAM. The Motorola DSP56002 is a DSP with a very rich instruction set that can perform complex data processing only limited by time and memory resources. The idea of the DSP and SRAM is to enable high-speed image co-additions. Once the image data is processed, the DSP writes into a 1Kx16bit output FIFO which buffers the data before being transferred to the timing board over the backplane. The transfer of data from the output FIFO to the timing board over the backplane is done in the same manner as with the standard CCD and IR video boards and does not involved any co-adder DSP involvement.
16.7 Preliminary Pin Assignment of SDSU-2 Detector Controller
Table 15 shows the preliminary pin assignment of connectors to the boards of the SDSU-2 Detector Controller.
Table 15: Preliminary Pin Assignment of SDSU-2 Detector Controller
|
Signal |
Description |
Board |
Connector |
Voltage Setting (V) |
|
BIASGATE |
Gate voltage of bias P-FET |
Video Board #0 |
VB015-1 |
+3.3 to +3.8 |
|
VRESET |
Control signal for resetting all the pixels |
Video Board #0 |
VB015-2 |
+0.50 to +1.0 |
|
BIASPWR |
Source voltage of bias P-FET |
Video Board #0 |
VB015-3 |
+5.0 |
|
VDDA |
Analog high power |
Video Board #0 |
VB015-4 |
+5.0 |
|
VDD |
Digital Power |
Video Board #0 |
VB015-5 |
+5.00 |
|
GND |
|
|
VB09-6 |
Gnd |
|
RESET CLOCK |
Control signal for resetting all the pixels |
Clock Board |
CB37-1 |
+4.0 to 0.15 |
|
VCLK CLOCK |
Master clock for the vertical register |
Clock Board |
CB37-2 |
+4.0 to 0.15 |
|
LSYNC CLOCK |
External Line Sync (horizontal register) |
Clock Board |
CB37-3 |
+4.0 to 0.15 |
|
FSYNC CLOCK |
External frame sync |
Clock Board |
CB37-4 |
+4.0 to 0.15 |
|
CLK1 |
Clock for horizontal register (Pixel) |
Clock Board |
CB37-5 |
+4.0 to 0.15 |
|
CLK2 |
Clock for horizontal register (Pixel) |
Clock Board |
CB37-6 |
+4.0 to 0.15 |
|
CLKB1 |
Clock for horizontal register (Pixel) |
Clock Board |
CB37-7 |
+4.0 to 0.15 |
|
CLKB2 |
Clock for horizontal register (Pixel) |
Clock Board |
CB37-8 |
+4.0 to 0.15 |
|
READ CLOCK |
Control signal for turning off the output |
Clock Board |
CB37-9 |
+4.0 to 0.15 |
|
RESETEN |
Optional control signal to reset the column bus to celldrain while no readout |
Clock Board |
CB37-10 |
+4.0 to 0.15 |
|
VOUT 1 |
Output amplifier 1 signal |
Video Board #0 |
VB09-1 |
|
|
VOUT 2 |
Output amplifier 2 signal |
Video Board #0 |
VB09-3 |
|
|
VOUT 3 |
Output amplifier 3 signal |
Video Board #1 |
VB19-1 |
|
|
VOUT 4 |
Output amplifier 4 signal |
Video Board #1 |
VB19-3 |
|
|
VOUT REFN |
Output Reference signal |
Video Board #0 and #1 |
VB09-2, VB09-4, VB19-2, VB19-4, |
|
The definition of the connector pin-naming scheme is as follows: VB09-X refers to pin X of the 9 pin detector output signal connector on Video board #0. VB19-X, refers to pin X of the 9 pin detector output signal connector on Video board #1. VB015-X refers to pin X of the 15 pin bias connector on Video board #0. CB37-X refers to pin X of the 37 pin connector on Clock Driver Board. The proposed grounding scheme is to connect the incoming ground to VB09-6 and case, VB09-8 and VB09-9 goes to VB19-6 and VB19-7 respectively, and VB19-8 and VB19-9 goes to CB37-22 and CB37-23. Note that the READ signal has been connected to a clock so that the output amplifier can be turned off when not reading out.
16.8 Non-Destructive Read Noise Reduction Algorithm
Non-destructive read noise reduction algorithm works by taking multiple reads of the pixel value during the exposure time and finding the slope of the best fitting straight line through the points using a least square fit. The algorithm (Chapman et al. 1990) to find the slope is
where Vi is the pixel value of sample i, n is the total number of samples, and dt is the time interval between samples. This is a much reduced form of the usual straight line fitting algorithm as it takes into account the fact that the values for t are all at fixed intervals which are known in advance.
The reduction in read noise for large n (Chapman et al. 1990) is described by
where sr is the read noise associated with a single read and sre is the equivalent read noise given by the noise reduction algorithm.