The detector is an SBRC CRC463 256 
256 InSb
array which is sensitive from 
0.9 
m
to 5.5 m. The array has four output channels
corresponding to four interlaced columns (12341234...). The array
is controlled by the SBRC ACE2 drive electronics which is mounted
close to the CASPIR dewar. Communications with the ACE2 is through an
RS-232 connection to MOPRA (Figure 20).
Figure 24: SBRC CRC463 detector array unit cell.
The CRC463 is a hybrid device in which the InSb detector material is
bump-bonded to a silicon multiplexer through indium bumps. The
multiplexer is a switched FET read-out device, which operates
differently to a CCD. The circuit schematic is shown in Figure
24. Each pixel (or unit cell) contains four FETs;
the two row select FETs and the reset FET (marked SW in
Figure 24) are switches which can be thought of as
closed when activated. The fourth FET (marked SF in
Figure 24) acts as a source-follower amplifier which
continuously samples the voltage on the detector node without
affecting its value. Vgg provides a load for the unit cell
source-follower FET. This load FET (marked SFL in
Figure 24) is located in the column biasing
circuitry. The output FET (also marked SF in
Figure 24) acts as a second source-follower amplifier
with its external 10 K 
load resistor in the ACE2 electronics
rack. The two column select FETs also act as switches.
Pixels in the array are sequentially addressed by pulsing column and
row shift registers which activate the column and row select FET
switches. Once a pixel is selected, the voltage on the detector node
can be non-destructively read via the source-follower amplifier signal
train, and the detector node voltage can then be optionally reset to
Vdduc by activating the reset FET switch by pulsing the 
rst
clock line. Note that the stored charge is not transferred across the
array like a CCD. Instead each pixel is sequentially reset and read.
This results in a time delay in the integration window across the
array of one frame readout time between the first and last pixels.
The array readout scheme permits the use of a variety of readout methods which are now described.